>SC5: Advanced IC Packaging and Chip/Package/Board Co Design Environment

SC5 title


Advanced IC Packaging and Chip/Package/Board Co Design environment

SC Duration

09.00-13.30. Refreshment break 11.00-11.30

SC instructor

Mr. Iyad Rayane

Application Engineer at Zuken, focusing on the Co-Design flow and Advanced Packaging solution with CR-8000.

SC instructor credentials


Mr. Iyad Rayane holds an Engineering diploma and a master’s degree in Microelectronics from the poly-technical institute in Grenoble, France.

He has more than 20 years of experience in the semiconductor field where he worked for 11 years as Application Engineer at Mentor Graphics for SoC design on Advanced process nodes. Prior to Mentor Graphics, he worked as EDA Engineer at ST Microelectronics developing RF and mixed signal design flows for big design houses. Iyad started his career in a startup in the Grenoble area specialized in the Mems design and modeling.

He is author and co-author of many scientific publications at international conferences.

SC objective


Traditional two-dimensional design tools often fall short when it comes to studying the structure and routability of the advanced packages required for today’s complex designs.

Virtual prototyping of the optimal floorplan is beneficial, along with the ability to access verification tools as early as possible in the process. Tools that support 3D system-level design, which also seamlessly connect with verification tools, can significantly improve the package design process.

A more intelligent approach to package design is one in which the chip, package and board can be designed simultaneously. A 3D chip, package and board co-design environment enables design and optimization of the interfaces between all three domains throughout the design flow.

SC outline


  • New design methodology for SiP
  • Support for wizards and parametric creation of IC’s, BGA package, and 3D wire-bond placement
  • Seamless connection of stacking IC’s and package on package (PoP)
  • Package-specific design rules with real-time 3D checks and view
  • Flip Chip I/O bump optimization
  • I/O ring synthesis capability guarantees package routability
  • “Tile-based” die bump placement and optimization
  • Tape-out quality automatic routing for chip RDL and package escape routing

SC target audience

The course is structured to be supportive to IC package designers and chip physical implementation engineers working on the top level implementation and the RDL routing in case of Flip Chip or Wafer Level packaging techniques.